IndustryPack® Modules are an important part of solutions for Embedded situations. Rugged, small, light ... just right for many applications. IndustryPack® Modules require a carrier to adapt them to the system. Dynamic Engineering has carrier solutions for a variety of formats.
If you want to use IndustryPack® modules with your PC104p or PCI-104 system PC104pIP is the choice for you. PC104pIP combines features you need with simplicity and speed. One IP module can be installed per carrier. Multiple carriers can be used in a stack. PC104pIP is highly integrated with the PCI and IP interfaces closely coupled within the same FPGA. As a result PC104pIP is faster, has a higher MTBF, and is easy to use. There are fewer initialization steps, and more features. With the Windows® driver; operation can be "plug and play". Linux driver also available. PC104p Chassis(s) is available
PC104p chassis to house your project.
PC104pIP is part of the IP Compatible family of modular I/O components. PC104pIP provides one IndustryPack® module site per PCI-104 stack position. PC104pIP acts as an adapter, converter, carrier, and bridge between the PCI bus and your IndustryPack® hardware.
PC104pIP is supported with Windows® compliant drivers for Win7 / 10 etc. as well as Linux and VxWorks support. The drivers come with a generic IP driver to allow use with "unknown" IP´s <=> IP´s that do not have a driver designed yet. For example, third party IP´s.
The PC/104p basic card size is smaller than the length of an IP module. The PC/104p specification allows for an added connector area of .5" on two edges. The "lower" connector area is used for the IP Module extension. The "upper" is used for the cable edge connector. The IP Module [type 1] when mounted is slightly smaller in height than the allowable component height for the PC104pIP plus the rear height of the board in the stack above the PC104pIP. If Type II or Type III modules are to be mounted or if the other cards in the stack have components in the rear mounting area then the PC104pIP will need to be mounted at the top of the stack or connector extenders used to create additional headroom.
Multi-board operation is supported. With multiple PC104pIPs in your system and unique cabling, sensors etc. for each stack position it is important to "know" which PC104pIP is which, and to properly control the IP modules mounted to them. A surface mount "dip switch" is provided to provide an identifier to the software. A specific PC104pIP can be matched with the PCI address allocated to make for deterministic control. The switch can be used for other purposes; configuration control or debugging for example. The switch values are available to be read via the PCI bus.
The IP position has a separate clock controller for 8 and 32 MHz operation. Glitch free operation means the frequency can be be changed on the fly. Series and parallel terminations with equal length traces insure clean clocks and coherant operation between the IP and the controlling state-machine. A well designed clock distribution is critical for reliable operation.
Resettable "self healing" fused filtered power. +5, +12, and -12V supported.
An Industry standard 50 pin [ribbon cable] headers is used with the IP IO connector. Ribbon cable or discrete wire cables can be interfaced directly with the PC104pIP. Alternatively the
HDRterm50 can be used to create a terminal block interface.
Three methods of resetting the IP are built into the PC104pIP. The IP can be reset from the control register within the FPGA via the software interface. The IP is reset on power-up via a supervisory circuit that guarantees the 200 mS minimum reset requirement in the IP specification. The resets only affect the IP.
An LED is provided to show IP slot activity. When accessed the LED is flashed. The Xilinx provides a "one shot" circuit to stretch the "on" time to make it visible. Power indicator LED´s [3] are provided. An additional eight user LED´s are available for debugging or other purposes.
IndustryPacks are usually 16 bit devices and the PCI bus supports 32 bits. PC104pIP accepts 32 bit PCI accesses and converts them into two 16 bit accesses with an auto-incremented or static address. One PCI access can be used to write to, or read from two IP locations or twice to one location. Byte, Word and Long Word accesses are supported to the 16 and 32 bit IP sites from the PCI bus.
The IP accesses are protected by a watch-dog timer. The timer is started at the beginning of each IP access. If the timer expires before the IP being accessed responds, a bus error internal to the PC104pIP is created. The PC104pIP responds normally to the host, not tying up the PCI bus, and provides status and an optional interrupt to alert the host to the problem with the IP. The Bus Error timer is useful in situations where the software may want to cause a bus error to find out what is installed or where a hung system would have consequences. Multi-threaded software operation is supported with separate bus error status in each of the slot control registers.
The PCI bus is defined as little endian and many IP´s have their register sets defined to operate efficiently with a little endian interface. The default settings on the PC104pIP are "straight through" byte for byte and D15-0 written to address 0x00 before D31-D16 written to address 0x02 when long words are written to 16 bit ports. Please note that any long word address can be used. The lower data is written to the lower address first, then the upper data to the upper address. The IP slot has a ByteSwap and WordSwap control bit to allow Byte and Word Swapping to be performed to accommodate alternate IP and OS requirements.
Byte Swapping accesses to a 16 bit port.
Connector positioning is compatible with
IP-Debug-Bus to allow the user to isolate and debug the control interface of an IP. The
IP-Debug-IO can be used in conjunction with the PC104pIP and IP-Debug-Bus to provide test-points on the IO signals and loop-back capability for the IP.
PC104pIP is an extended temperature board. This extended or "Industrial Temp" design has components rated for -40C to +85C minimum. This temperature range will need to be derated based on your chassis thermal situation.