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PC104p-SpaceWire
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Now shipping: Updated SpaceWire Capabilities
PC104p-SpaceWire Description
- PC104p bridge to SpaceWire with 4 channels
- Designed for rapid user integration with included reference software
- Large User allocatable memory [256 MBytes] with 32 Mbyte default per port
- 8 Independent Scatter-Gather DMA engines to support the 8 SpaceWire ports
- Fast: 1-200 MHz. with autobauding on Rx ports. Each Tx port has a separate PLL reference plus divider
- Low latency, FIFO based design
- Time Code support
- Easy-to-use: heirachical design featuring a direct memory map
- 1 year warranty standard. Extended warranty available.
- Extended Temperature standard.
- ROHS and Standard processing available
Utilize SpaceWire to communicate with European Space Agency and NASA equipment utilizing the ECSS-E-ST-50-12C specification. SpaceWire is configured using routers to create a heirarchical point-to-point system with high speed parallel paths.
PC104p--SpaceWire implements SpaceWire in a convenient PC104p and related [PCI-104] form factors. Four fully independent and highly programmable LVDS IO ports are provided by the PC104p-SpaceWire design. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point with token based flow control. With the SpaceWire protocol it is easy to build a heirarchical architecture system with routers or a home-run wired system. Your equipment can interact with any other node in the system. PC104p-SpaceWire provides a bridge from PCI ⇔ SpaceWire. Port based DMA offloads the CPU and increases performance in your system. Time Code support provides a complete solution. Please refer to the manuals tab for detailed information
Each port has memory to support RX and TX functions. BK models have more than 32 MBytes per port. The memory is organized as FIFOs 32 bits wide to optimize data transfer from the PCI/PCIe bus. The FIFOs are a combination of internal block RAM and attached DDR memory.
Multiple programmable interrupts are avaialble. The FIFO flags are supported for interrupt driven or polled operation. Programmable Almost Full, Programmable Almost Empty, plus Full, Half Full, and Empty. The programmable flags can be set to any debth to allow software a programmable delay from event to empty or full. The interrupts can be very useful when sending or receiving messages larger than the FIFO size. In addition interrupts and status are available for packet completion, various error conditions etc.
The FIFO design supports loop-back and can be used for Built In Test [BIT]. Memory can be accessed with target or DMA accesses. The host side interface is optimized with independent DMA controllers for each port [8 total]
SpaceWire features automatic link testing when a node is brought on line - released for operation via software. The transmitter sends NULLs until NULLs are received and then sends FCTs until FCTs are received. The initial frequency is specified [ECSS-E-ST-50-12C] to be 10 MHz. Once the auto link test has passed, the hardware can switch to the programmed rate. A local oscillator is used to supply the 10 MHz reference clock for initialization. A programmable PLL is used to support operation once the link is established. The PLL is programmed via software and is referenced to the oscillator.
The SpaceWire protocol has flow control. The local memory on PCIe-SpaceWire will not overrun. The buffering issue may be upstream - if there is an unbuffered or under-buffered data source that will loose data if the link is throttled back the large storage capability will help. The larger FIFOs will provide more room to accumulate data if the system is not ready to allow PCIe-SpaceWire to DMA transfer immediately. The DMA transfers are higher bandwidth than the SpaceWire transfers allowing the system to catch-up once the DMA transfers restart. At 100 MHz and 80% data transfer the 8Mx32 FIFO will provide about 3.2 seconds of data storage per port. The host would have to ignore the PC104p-SpaceWire interrupt requests for longer than 3.2 seconds before throttling would occur. In most systems this is sufficient time to stay out of the throttled mode. To unload a full FIFO with DMA running it will take 8M/50M = .16mS => the unload to load multiplier is stongly in favor of the host side allowing the host to catch-up to the SpaceWire link once the delaying event has passed. The actual DMA time will be a bit higher due to system interaction to initialize etc. The actual transfer time is shown.
The Dynamic Engineering software packages support each of the board features including PLL programming - supply the .jed file and our SW takes care of programming, FIFO loop-back, external loop-back etc. The reference software is a great starting point for your system software.
Model -BK is recommended for new projects and projects that want an upgrade. For PC104p-SpaceWire the K revision is now depricated and only available on special request.
PC104p-SpaceWire is supported with the DESWBO Dynamic Engineering SpaceWire BreakOut tool for debugging SpaceWire systems, cables, and the DESWCB Dynamic Engineering SpaceWire Connector Board which provides a SpaceWire Cable to system cable interface.
If your situation demands a custom application then we will update the Xilinx FPGA. Send us your timing and we will send you the interface.... email us your wish list or call today!
PC104p-SpaceWire-BK Block Diagram
Model BK diagram shown
The standard timing uses the data and strobe to transmit and to receive the data. The data is transmitted as a command or data. The strobe provides the transitions for clocking when the data is unchanged between adjacent bit times.
PC104p-SpaceWire Standard Timing
PC104p--SpaceWire implements SpaceWire in a convenient PC104p and related [PCI-104] form factors. Four fully independent and highly programmable LVDS IO ports are provided by the PC104p-SpaceWire design. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point with token based flow control. With the SpaceWire protocol it is easy to build a heirarchical architecture system with routers or a home-run wired system. Your equipment can interact with any other node in the system. PC104p-SpaceWire provides a bridge from PCI ⇔ SpaceWire. Port based DMA offloads the CPU and increases performance in your system. Time Code support provides a complete solution. Please refer to the manuals tab for detailed information
Each port has memory to support RX and TX functions. BK models have more than 32 MBytes per port. The memory is organized as FIFOs 32 bits wide to optimize data transfer from the PCI/PCIe bus. The FIFOs are a combination of internal block RAM and attached DDR memory.
Multiple programmable interrupts are avaialble. The FIFO flags are supported for interrupt driven or polled operation. Programmable Almost Full, Programmable Almost Empty, plus Full, Half Full, and Empty. The programmable flags can be set to any debth to allow software a programmable delay from event to empty or full. The interrupts can be very useful when sending or receiving messages larger than the FIFO size. In addition interrupts and status are available for packet completion, various error conditions etc.
The FIFO design supports loop-back and can be used for Built In Test [BIT]. Memory can be accessed with target or DMA accesses. The host side interface is optimized with independent DMA controllers for each port [8 total]
SpaceWire features automatic link testing when a node is brought on line - released for operation via software. The transmitter sends NULLs until NULLs are received and then sends FCTs until FCTs are received. The initial frequency is specified [ECSS-E-ST-50-12C] to be 10 MHz. Once the auto link test has passed, the hardware can switch to the programmed rate. A local oscillator is used to supply the 10 MHz reference clock for initialization. A programmable PLL is used to support operation once the link is established. The PLL is programmed via software and is referenced to the oscillator.
The SpaceWire protocol has flow control. The local memory on PCIe-SpaceWire will not overrun. The buffering issue may be upstream - if there is an unbuffered or under-buffered data source that will loose data if the link is throttled back the large storage capability will help. The larger FIFOs will provide more room to accumulate data if the system is not ready to allow PCIe-SpaceWire to DMA transfer immediately. The DMA transfers are higher bandwidth than the SpaceWire transfers allowing the system to catch-up once the DMA transfers restart. At 100 MHz and 80% data transfer the 8Mx32 FIFO will provide about 3.2 seconds of data storage per port. The host would have to ignore the PC104p-SpaceWire interrupt requests for longer than 3.2 seconds before throttling would occur. In most systems this is sufficient time to stay out of the throttled mode. To unload a full FIFO with DMA running it will take 8M/50M = .16mS => the unload to load multiplier is stongly in favor of the host side allowing the host to catch-up to the SpaceWire link once the delaying event has passed. The actual DMA time will be a bit higher due to system interaction to initialize etc. The actual transfer time is shown.
The Dynamic Engineering software packages support each of the board features including PLL programming - supply the .jed file and our SW takes care of programming, FIFO loop-back, external loop-back etc. The reference software is a great starting point for your system software.
Model -BK is recommended for new projects and projects that want an upgrade. For PC104p-SpaceWire the K revision is now depricated and only available on special request.
PC104p-SpaceWire is supported with the DESWBO Dynamic Engineering SpaceWire BreakOut tool for debugging SpaceWire systems, cables, and the DESWCB Dynamic Engineering SpaceWire Connector Board which provides a SpaceWire Cable to system cable interface.
If your situation demands a custom application then we will update the Xilinx FPGA. Send us your timing and we will send you the interface.... email us your wish list or call today!
Model BK diagram shown
The standard timing uses the data and strobe to transmit and to receive the data. The data is transmitted as a command or data. The strobe provides the transitions for clocking when the data is unchanged between adjacent bit times.
PC104p-SpaceWire Features
Size
Standard dimension PC104p or PCI-104 card - 3.550in x 3.775in
Transmit Speeds
10 MHz initial rate per SpaceWire Specification. Software selectable secondary rate for transmit channel. Max. BK models rated at 200 MHz. Oscillator and programmable PLL combined for user frequency support.
PCI Speed
Standard 33 MHz. operation. DMA support or standard R/W operations, DMA is independent per port - each port has a separate controller to allow long data transfers with minimal CPU overhead and increased performance.
PCI Access Width
Standard 32 bit operation supported
Software Interface
PC104p registers are read-writeable. Transmit and Receive functions separated.
Interrupts
Transmit and Receive state-machines, FIFO Programmable almost empty [transmit] and programmable almost full [receive] have programmable interrupts. Status can be polled for non-interrupt driven operation as well. Time Code interrupt.
Signaling
LVDS interface devices are utilized.
IO Interface
Available via the 9 Pin MDM connectors as specified in ECSS-E-ST-50-12C. The differential IO is properly routed with controlled impedance, and matched lengths on each of the pairs.
Interface
ECSS-E-ST-50-12C specification compliant. Time Code supported.
Specification
PC104p specification compliant
Power
5V and 3.3V from PC104p connector with 2.5V, 1.2V converted with on-board regulators.
Memory
Separate FIFOs are provided for TX and RX of each port. Internal Block RAM plus DDR memory - 32 MBytes is standard for all ports.
Statement of Volatility
DIP switch
An 8 position switch is available to select stack position plus allow for configuration control, multiple PC104p SpaceWire boards, and to facilitate integration
STEP
STEP files are available to support your system integration. Please contact sales@dyneng.com for this option.
PC104p-SpaceWire Benefits
Speed
PC104p-SpaceWire is optimized for serial interfacing requirements. The FIFO memories and programmable interrupts off-load the CPU from most of the management other implementations require. FIFO access is optimized for the PCI bus further reducing overhead by speeding up the data transfer. On the IO side the PC104p-SpaceWire has independent and interconnected port functions. All ports can operate at maximum rate in parallel.
Price
PC104p-SpaceWire is available off-the-shelf at a reasonable price. Custom versions can also be arranged. PC104p SpaceWire is easily programmed to implement new functions. Previously implemented "custom designs" are available too. Without the costs of schematic level design, layout, debugging etc. A modified SpaceWire will represent a large cost and time savings in your budget.
Ease of Use
PC104p-SpaceWire is easy to use. Make use of our drivers for automatic detection, initialization, setting frequecies, transferring data etc. Built in loop-back capabilities and reference software help with integration into your system. Windows® Linux and VXWorks driver(s) available.
Availability
Dynamic Engineering works to keep PC104p-SpaceWire in stock. Send in your order, and in most cases have your hardware fast. With custom designs a few weeks of design is usually required. We can support immediately with the std version, then send updated FLASH files later to help get your project going - right away.
Size
PC104p-SpaceWire is a standard single height PC104p card, and meets the PC104p mechanical specifications. PC104p-SpaceWire can be used in all PC104p positions [universal voltage]
PC104p Compatibility
PC104p-SpaceWire is PC104p compliant per the PC104-Plus specification.
PCI Compatibility
PC104p-SpaceWire is PCI compliant. You can develop with a PCI (e) to PC104p adapter - PCI2PC104p, PCIBPC104pET etc.
Part Number: PC104p-SpaceWire
Ordering Options
-
Order combinations of the options by simply adding the extension(s) to your order request.
PC104p-SpaceWire -BK - with 32 Mbytes FIFO per port (Rx and Tx separately), standard SpaceWire [ECSS-E-ST-50-12C] timing and protocol. Independent DMA and Timecode support. Four ports . PCI and ISA connector installed. ISA connector is pass through only.
PCI-104-SpaceWire-BK - ISA connector not installed.
-Monitor - Change FLASH to Monitor function to capture data streams on Ports 0,1. Application manages HW and stores data to file. Each packet is pre-pended with time tag, packet number and size.
-CC - add Conformal Coating
-ROHS - add ROHS processing
PC104p-SpaceWire Drivers
Software Support is supplied in the form of Windows, Linux, and VxWorks packages. The manuals are available on the SpaceWire Summary page. Windows and Linux are included in purchase. VxWorks requires an additional fee.