ccPMC-HOTLink

HOTLink is used in applications demanding high speed and high reliability including sonar, radar, other scanning applications, seismic, oil exploration etc. Alternate purposes would include high speed buses between equipment or within equipment for command and control, data transfer etc. ccPMC-HOTLink is a conduction cooled PMC card with 6 HOTLink receiver/transmitter pairs plus 12 differential IO. Each of the HOTLink channels is supported with a separate DMA transfer engine plus local memory.

The HOTLink protocol implemented provides positive emitter coupled logic (PECL) data inputs and outputs. The receive side can be direct or transformer coupled. The transmit byte rate is determined by the programmed frequency of the PLL clock A output. This clock is multiplied ten times by the HOTLink transmitter to send the transmit byte data stream which is expanded to 10 bits by the internal 8B/10B encoder. The PLL is programmed via software over a serial I2C interface.

Up to six independent HOTLink channels are provided. Each HOTLink channel has four differential I/O signal pairs: A HOTLink differential PECL output, a HOTLink differential PECL input and two bi-directional differential RS-485 lines. The RS-485 IO each have independent direction and termination controls to allow programmable operation with many IO requirements. The 485 IO can be used for an alternate purpose and is directly controlled by the FPGA

The HOTLink input can be transformer-coupled into a dual 50Ω terminations referenced to 1.8 volts. The signals are then AC-coupled into the HOTLink receiver inputs. The HOTLink output is AC-coupled after the bias/termination network. Both AC coupling stages can be replaced for a DC coupled system.

ccPMC-HOTLink features a Spartan 6 FPGA. The FPGA allows for a lot of internal memory and more complex data manipulation in HW. The memory is typically used for FIFOs or RAM. The FIFOs can be accessed by single-word and DMA burst transfers. A FIFO test bit in each channel control register enables the data to be routed between the transmit and receive FIFOs for a full 32-bit path. The ports are supported with 12 independent DMA engines. Local arbitration keeps the data moving efficiently. DMA transfers can be programmed for any size transfer from very small to multiple megabytes using the scatter gather capable programming model.

This PMC module is conduction-cooled and has no front panel connector. All I/O connections are routed through PN4. All parts are industrial temp or better [-40C <=> +85C]. Conformal coating, thermal gluing and thermal foam are available options help adapt to your environment.
ccPMC-HOTLink Block Diagram

PMC Modules require a "carrier" in most cases to adapt them to the system. Dynamic Engineering has carrier solutions for a variety of formats.
PCIe implementations can be done with the PCIeBPMCX1 and PCIeBPMCX2.
PCI implementations can be done with the PCI2PMC and PCIBPMCX2.
cPCI 3U is supported with the cPCIBPMC3U64
cPCI 6U is supported with the cPCIBPMC6U.
PCI-104 is supported with the PCI104p2PMC.

PMC´s are independently specificed through VITA for the form factor, connectors and pinouts of the PCI signaling; you can use with any carrier from any vendor that supports standard PMCs. To make it even easier Dynamic Engineering PMCs feature a universal voltage PCI design to allow operation with VIO set to 3.3 or 5V.

It all starts with the PCB [Printed Circuit Board]. Quality design and quality materials are required to meet the strenuous requirements of many of our implementations. You can do the job quickly or you can do the design correctly. We pride ourselves on taking the time to put the extra work into our layouts. The quality goes in before the parts go on. In addition to routing strategy and layer counts, Via size, plating requirements, break-out trace widths, and materials are areas where quality comes into play. The via size and method of trace attachment to the via affect the signal shape and reliability. Using tear-drop trace connections to pads, via´s and through hole components enhance the reliability and minimize the impedance discontinuity resulting in a cleaner signal. The combination provides better vibration endurance than smaller vias and traces would provide. The design has several power planes with sufficient copper weight and coverage to provide the references required for the routing plus the current and voltages needed by the various devices on the board. The larger features make the design work more difficult since there is less room to "play with" and the end result is worth it. Since 1998 Dynamic Engineering designs have enjoyed an excellent track record for reliability.

The PCI interface has a published set of requirements for compliance which restrict length, impedance, loading and other factors. ccPMC-HOTLink is compliant with the PCI Specification. The IO section has requirements based on the IO type and the purpose for the IO. A very conservative approach has been taken to allow operation with any client requirement. The design has matched length connections from the FPGA ball to the seating plane of the connector. The lengths are matched to the "mil". The Impedance is controlled and the signals routed with proper spacing to avoid cross talk etc. The other features including memory, PLL, oscillator, and power supplies are implemented within the PCB to exceed the operational requirements for those devices.

Clock options are frequently a major factor in embedded designs. Getting the right reference to the right part of the design and allowing for local control of exact frequencies. With a PLL providing 4 programmable outputs, reference oscillator, internal DCMs and buffering plus programable dividers instantiated within the VHDL. The PLL can be programmed to "any" fixed frequency, the DCM used to create phase variations, and local dividers to allow on-the-fly channel based frequency changes.

"Channelized DMA"™ is an important feature of the ccPMC-HOTLink design. With "Channelized DMA"™ you have a separate DMA engine for each transmitter and each receiver within each port. Each state-machine can be serviced independently with DMA without requiring intervention from the host. Large data transfers can happen between multiple connections while the CPU is off doing something else. In non-channelized designs the CPU will have to intervene each time a different port needs to be serviced. With a channelized approach the hardware takes care of the local arbitration, and eliminates the intervention for better system performance and less latency.