PCI-ECL-II



PCI-ECL-II - upgraded with Spartan 6 FPGA, 8Mx32 SDRAM per channel, 2 channels plus 20 ECL TX , 20 ECL RX, and 12 TTL IO





Do you feel the need for speed? Differential ECL / NECL is still the interface of choice for high speed in noisy environments. PCI-ECL-II is an upgrade to the original PCI-ECL design. The IO connector pinout is maintained to allow ease of porting to the new platform. 20 ECL Inputs and 20 ECL Outputs plus 12 TTL IO are controlled via the FPGA. NECL, LVPECL and other ECL translators can be installed to meet IO requirements. The IO are matched length and impedance controlled. The Spartan VI FPGA provides the PCI interface, SDRAM interface, and IO interface with plenty of room for control, storage, filtering. and other control functions. With the SDRAM controller design, data can be stored for retransmission and looped if desired. The SDRAM can also be configured for FIFO like data handling. All options are selectable with software.

PCI-ECL-II features integrated PCI interface with DMA support coupled to your design requirements. Dynamic Engineering can design a solution for you or you can implement one too. The Xilinx is reconfigurable, and supported with reprogrammable FLASH. The reference design contains the PCI interface with DMA support, SDRAM, IO and PLL. The reference design is supported with a Windows® driver which has the capability to support your changes without having to write a new driver. We can of course make a new driver with direct calls to your hardware design implementation. The user reference design is under construction at this time. The features are complete - we need to turn the PCI and DMA section into a "black box" to allow transfer to clients without NDA issues. Dynamic Engineering can perform user designs for our clients at this time.

The ECL IO is carefully routed to provide 100 ohm differential impedance, and matched length from the pin edge on the D100 connector to the Xilinx [BGA] Ball. All of the TX are matched, and all of the RX are matched to allow for high speed designs with tight timing requirements. Several ECL input bits are tied to clock capable input pins on the Xilinx to allow for external reference clocks.

The Xilinx is supported by a programmable PLL. The PLL is programmed with a serial bus via the Xilinx control register set. The Windows® driver handles this function. We recommend using the Cypress calculator to determine the PLL settings. The PLL supplies four clocks to the Xilinx which can be used for custom state-machine support.

In addition to the PLL, a customer selected oscillator position is supplied. The default oscillator frequency is 50 MHz. and is used as the reference for the PLL. The oscillator frequency can be changed if required.

The ECL section has 20 inputs and 20 outputs. The state-machine can be programmed to use any number of the IO. The remaining IO can be used for a general purpose parallel port. Serial and Parallel interfaces can be implemented. For example, with a 4 wire serial interface a 16 bit parallel port will be available.

The external "FIFO" is used to store data from reception or for transmission. The memory is large enough that the IO can operate without interruption. The system can "go away" and not under or over-flow the memory. The SDRAM is 32 MBytes in size per channel. There are two channels on the board. Assuming a TX/RX channel on each SDRAM and allocating ½ of the memory to TX and to RX there are 16 MBytes per function. Further, assuming a continuous transmission is being supported, a 100 Mbit/sec serial data link, and DMA operation in use; the memory will support 1.34 seconds of system interruption. Similarly the Rx side can operate for 1.34 seconds before overflowing [assuming no handshaking in the design]. The memory can be allocated in software providing for asymmetrical operation, all on TX or all on RX for example.

The SDRAM can also be configured to retransmit data. The memory can be partitioned into a header, body, and tail. The body can be repeated a programmable number of times. The header => body=>tail loop can then be repeated or stop at completion. All under software control. In continuous mode interrupts can be generated at the end of each major loop. The boundaries are programmable to allow for customized sizes.


The Internal FIFO is to support DMA. The data is pipelined into or out of the FIFO under control of the scatter gather DMA engine. Data can also be moved with non DMA read or write operations. Data stored into the FIFO is moved to the main memory (SDRAM) and vice-versa. A state-machine moves the data with a burst transfer when there is sufficient data to move, and single transfers when near the boundary conditions. The state-machine for the data transfer operates autonomously. Each function has a separate DMA engine to allow for parallel TX and RX operation without software intervention.

Multi-board operation is supported. With multiple PCI-ECL-II´s in your system and unique cabling, sensors etc. for each slot it is important to "know" which PCI-ECL-II is which. A surface mount "dip switch" is provided to provide an identifier to the software. A specific PCI-ECL-II can be matched up with the PCI address allocated to make for deterministic control. The switch can also be used for other purposes; configuration control or debugging for example. The switch values are available to be read via the PCI bus.

The reprogrammable FLASH memory stores the Xilinx design file. The JTAG header is used to load the FLASH using the Xilinx standard IMPACT® software and download cable.

PCI-ECL-II can be ordered with a standard IO control design or updated with a customer specific design via the FLASH. If you prefer to design your own interface; the -STE3 version HTML is available as part of the engineering kit. When Dynamic Engineering creates a new design the new design is named PCI-STANDARD-II--Customernamedesignnumber. For example the PCI-NECL-XG1 is the first NECL based version done for the XG company on the previous revision of the ECL design. The new design will be fully documented and the manual available from this web page. Dynamic Engineering is available to engineer customer specific solutions using PCI-ECL-II and other Dynamic Engineering designs. Please contact engineering@dyneng.com or call and ask to speak with one of our knowledgeable technical sales staff to help you with your implementation requirements.

The IO is brought to a "D100" connector. The connector on the PCI-ECL-II is a available in the standard right angle or a vertical mount. The right angle connector mounts through the bezel allowing for IO outside of the chassis. The vertical connector is used with a blank bezel and is optimized for internal to the chassis IO requirements. The mating connector is the AMP 749621-9 or 719109-7. Dynamic Engineering has cables and a break-out for this connector. HDEterm100 can be used to create a terminal block interface. HDEcabl100 is the standard cable. Customer specific cables can be manufactured. Please forward your connector and pin assignment requirements if you are interested in custom cables. In addition Dynamic Engineering has a "cross over" cable which can be used to interconnect two PCI-ECL-II cards or to connect to your equipment if you adopt the connector definitions that we used. The Pinouts are available within the manuals.


Block Diagram of PCI-ECL-II


PCI-ECL-II Features

  • Size
  • 1/2 size PCI card.


  • IO
  • 20 ECL TX, 20 ECL RX, 12 TTL IO.


  • Clocks
  • PLL [Cypress 22393], PCI, OSC, External clock sources are available for use


  • Xilinx
  • Spartan 6 100 LX


  • PCI Bus
  • 33 MHz 32 bit PCI bus implementation with DMA. Universal Voltage keying.


  • Cable interface
  • D100 connector. Pinout in manual. Right angle standard, Vertical mount available.


  • Software Interface
  • Control registers are read-writeable. Windows® XP/2000 drivers available.


  • Interrupts
  • Multiple status and operation based programmable interrupts are provided. FIFO almost empty, FIFO almost Full, transmit complete, receive complete etc.. All are routed to INTA on the PCI bus. Control and status registers are provided to control and to determine the source of the interrupt


  • Power Requirement
  • On board power supplies create +3.3, +2.5, +1.2, and -5V.


  • LED´s
  • Voltage monitor circuits show operational voltages present


  • DIP switch
  • An 8 position switch is available to support multi-board operation or other user defined purposes.


  • Humidity
  • The PCI-ECL-II is a standard industrial grade board, able to handle the usual 10-90% non-condensing humidity rating. If you need to have a board used in a more harsh environment, ask to have humi-seal after final test.


  • Weight
  • Approximately 5 oz for non Humi-sealed board.


  • Volatility
  • Download the Statement of Volatility in PDF format.


    PCI-ECL-II Benefits

  • Speed
  • PCI-ECL-II is designed for speed. The PCI bus is supported with DMA and an internal holding FIFO. The State-Machines interoperate with the SDRAM and support FIFO's [block RAM]. The NECL IO can operate up to 250 MHz. A separate state machine keeps the data flowing between the internal FIFO´s and SDRAM. True pipelined operation can be implemented between the system memory and the external device.


  • Price
  • PCI-ECL-II combined with custom design is an attractive package.


  • Ease of Use
  • PCI-ECL-II is easy to use. Windows® Drivers are available. Please download the manual(s) and see for yourself. The engineering kit provides a good starting point for a new user.


  • Availability
  • PCI-ECL-II when outfit with the standard NECL IO is a standard product for Dynamic Engineering. Most likely there will be a small quantity immediately available from stock. For custom design work to support your requirement a small additional time will likely be required. We can ship the boards with a similar VHDL set to allow early initegration while the customized VHDL is developed.


  • Size
  • PCI-ECL-II is a 1/2 size PCI board which conforms to the PCI mechanical and electrical specifications. Eliminate mechanical interference issues. Fits in the small form factor chassis as well as standard [full length].


  • PCI Compatibility
  • PCI-ECL-II is universal voltage PCI compliant device. PCI-ECL-II can be expected to work in any PCI compliant backplane.


    Ordering Information
    PCI-NECL-II....................Standard board
    PCI-NECL-II-1..................Alternate vertical connector installed for internal wiring


    Customized Versions

    PCI-NECL2-STE3
    Customer: Singapore Technologies Electronics Limited

    Custom Parallel interface. 8 bit parallel data path with reference clock and enable. Data valid on falling edge of clock, enable active high. DMA support, 12 bits uncommitted TTL IO. STE3A is recommended for new designs.
    STE3 is available for previously integrated systems.
    Download the
    PCI-NECL2-STE3 Hardware revision A/B Manual in PDF format.
    Download the PCI-NECL2-STE3 Windows® revision A/B Manual in PDF format.


    PCI-NECL2-STE3A
    Customer: Design Update

    Custom Parallel interface. 8 bit parallel data path [NECL input and output]with reference clock and enable. Data valid on falling edge of clock, enable active high. DMA support, 12 bits uncommitted TTL IO. Updated with higher performance memory operation, increased FIFO size, added status, and operational enhancements. Recommended for new designs rather than STE3 Client tested with standard and external chassis.
    Download the PCI-NECL2-STE3A Hardware revision A1 Manual in PDF format.
    Download the PCI-NECL2-STE3A Linux revision 1.0.3 Manual in PDF format .


    PCI-NECL2-RTN10
    Customer: Raytheon

    Custom Parallel interface. 8 bit parallel data path [NECL input and output] with reference clock and enable. Data valid on programmable edge of clock, enable active high. Programable use of enable. DMA support, 12 bits uncommitted TTL IO. Updated with higher performance memory operation, increased FIFO size, added status, and operational enhancements. Recommended for new designs. Client tested with standard and external chassis.
    Download the PCI-NECL2-RTN10 Hardware revision A1 Manual in PDF format.
    Download the PCI-NECL2-STE3A Linux revision 1.0.3 Manual in PDF format . RTN10 version in the works


    Engineering Kits

    Dynamic Engineering provides Engineering Kits to help our customers have a successful and quick integration. Engineering Kits will save time and money with decreased T&I. We recognize that different customers have different needs. The Engineering Kits are standardized in description to help with selection. The kits are segmented to allow for customers who only need hardware support, software support or a mixture. The Engineering Kit is highly recommended for first time buyers. The kit pricing is discounted to encourage their use.

    PCI-ECL-II-Eng .......... Hardware Support Engineering Kit includes:
    Board level Schematics [PDF], HDEterm100, HDEcabl100

    PCI-ECL Drivers.......... Software Support Only Windows®XP and 2000 compliant drivers for the PCI-ECL-II.
    Please see the Driver manual for the specifics of using the driver. Previously developed drivers are free with purchase of PCI-ECL-II.


    PLL Support
    Download the CyberClocks R2.01.00 software
    right click on the above link to download and save the cyberclocks zip folder to your target


    Related Products
    HDEterm100 100 position terminal block with D100 cable interface for PCI-ECL
    HDEcabl100 PCI-ECL compatible cable
    .

    HDEcabl100-ECL-crossover
    The PCI-ECL cross-over cable has cross over connections for the "ECL out" and "ECL in" [19-0] differential pairs plus straight through connections for the TTL [11-0] and ground. The cable allows direct board to board connections with a common pinout on the board side. Download the PCI-ECL crossover cable pinout in PDF format.
    Straight through cables are also available (HDEcabl100). Both are compatible with the PCI-ECL-II and HDEterm100.


    Custom, IP, PMC, XMC, PCI, PCIe, VME, VPX, PC104p, cPCI, cPCIe Hardware, Software designed to your requirements


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