PC/104p-BiSerial
PCI-104 and PC/104p Compatible Bi-Directional Serial Data Interface
Front View - shown with development header installed



Rear View- shown with development header installed




Please note that new designs should use the PC104p-BiSerial-III

The PC/104p BiSerial has been ported from the PMC BiSerial II. Building on the knowledge and experience gathered from multiple IP and PMC BiSerial implementations and adding in the latest technology has created the PC/104p--BiSerial. The BiSerial features completely isolated FIFOs with 32 bit ports for increased adaptability and performance. 16 - 40 MHz 485 buffers with programmable termination and direction can be configured to your systems requirements. An expanded faster FPGA will implement the most complex state-machines. Many of the designs implemented for the PMC and IP versions can be ported to the PC/104p.

The Biserial family has been used for many applications including: telemetry, manchester encoding and decoding, command and control, interface simulation, "glue" between incompatible systems, radar systems, industrial interfaces, inventory, optical recognition, airborne, ground based, and ship based.

An example of a simulation application is the use of a BiSerial to simulate or emulate an expensive piece of equipment that is required for test. The BiSerial can be used to simulate a target system like an airplane, missle or other vehicle to interact with the equipment that would be connected to the target system. Many times having a computer based interface is more convenient than having the actual target application. Test, debugging, diagnostics etc. can be computer driven using the BiSerial much more easily than the "real" system in many cases. Consider the BiSerial family for your interfacing and support requirements.

Options include LVDS, DAC and ADC channels. There are 4 DAC, and 4 ADC channels which can be populated with 200 KHz. 16 bit devices. The analog and TTL IO can use the external FIFOs or the internal Block RAM when smaller FIFOs are needed.

Two fully independent and highly programmable RS-485 / RS-422 IO channels are provided by the PC/104p-BiSerial design. The channels are supported by two independent state-machines created within the Xilinx FPGA. The two channels can have the same or different protocols. Manchester encoding and decoding, standard serial [UART], control, command, instrumentation, and custom protocols can be implemented.

Each channel has a separate FIFO with 16Kbytes standard and up to 512Kbytes as an option. The FIFOs are 32 bits wide to optimize data transfer from the PCI bus. The interface is optimized to minimize the latency on the PCI bus. The data transfer size can be anything on the IO side. The FIFOs support internal loop-back testing. The loop-back test can be used for BIT, and for software development. The programmable FIFO flags are supported on both sets of FIFO. Programmable Almost Full, Programmable Almost Empty, plus Full, Half Full, and Empty. The programmable flags can be set to any debth to allow the software a programmable delay from event to empty or full. The interrupts can be very useful when sending or receiving messages larger than the FIFO size. The interrupts are programmable and provisions are made to allow polling.

The PC/104p-BiSerial has 16 transceivers which can be used for any combination of input and output functions. Parallel and serial data, multiple channels, and different hand-shaking schemes can be implemented with the quantity of IO on the PC/104p-BiSerial. The transceivers support up to 40 Mhz clock and data rates.

Eight TTL IO are provided for flexibility, and to remove the need for an additional card when only a few bits are needed. The state-machines can be coupled to the TTL IO or they can be used as a separate parallel port or other function.

The base design has a PLL, oscillator position, and PCI clocks to choose from for a variety of clocking options. Custom oscillator frequencies can be installed when an exact frequency is required. The PLL can be used to create custom frequencies. The PLL is programmable via I2C bus. The driver supports programming the PLL.

If your situation demands a custom application then we will update the Xilinx FPGA. Send us your timing and we will send you the interface.... email us your wish list or call today!

PC/104p-BiSerial Block Diagram



The standard timing [-IO] uses the clock and strobe to transmit and to receive the data. Data is shifted to the next bit on the falling edge and valid of the rising edge of the clock. The Set-up and hold are approximately 50/50 for a very stable interface. The clock edge can be reversed, the strobe can be made to be active high, the data width can be changed, the bit order can be changed etc.. Frequently parity or other error correction provisions are added. If the standard or one of the customer specific protocols will work for you - fantastic - and if not please let us know what you need and we can implement it for you.

PC/104p-BiSerial Standard Timing




PC/104p-BiSerial Features

  • Size
    		•  Standard PC/104p

  • IO Speeds
    		•  40 MHz RS485 signaling supported. LVDS transceivers rated at 200 MHz. Xilinx may limit the top rate, 200 KHz ADC, 200 KHz DAC, TTL is Xilinx driven.


  • Clocks
    		•  PLL [Cypress 22393], PCI, OSC, External clock sources are available for use

  • PCI Speed
    		•  Standard 33 MHz. operation

  • PCI Access Width
    		•  Standard 32 bit operation supported.

  • Software Interface
    		•  Registers are read-writeable. Transmit and Receive functions separated.

  • Interrupts
    		•  Transmit and Receive state-machines, FIFO Programmable almost empty [transmit] and programmable almost full [receive] have programmable interrupts. Status can be polled for non-interrupt driven operation as well.

  • Signaling
    		•  16 RS-485 / RS-422 compatible IO are provided. Any combination of transmit or receive channels can be created. Programmable termination. LVDS IO are available on all channels. Up to 4 DAC channels and/or 4 ADC channels can be added. Each channel can operate at 200 KHz and has a 16 bit resolution. 8 TTL IO are provided.

  • IO
    		•  The IO is available via the 50 pin right angle header. The differential IO is properly routed with controlled spacing and matched lengths on each of the pairs.

  • Interface
    		•  The -IO version of the PC/104p BiSerial has support for Data, Clock and Strobe. Custom programmed interfaces are available with other options.

  • Power
    		•  +5 only. 3.3 and 2.5 converted with on-board regulator.

  • Memory
    		•  Separate FIFOs are provided for both channels.
    4K x 32 is standard. 8K, 16K, 32K, 64K, and 128K x 32 are available.





    PC/104p BiSerial Benefits

  • Speed
    		•  The PC/104p BiSerial is optimized for serial interfacing requirements. The FIFO memories and programmable interrupts off-load the CPU from most of the management other implementations require. The FIFO access is optimized for the PCI bus further reducing overhead by speeding up the data transfer. On the IO side the PMC BiSerial has independent channel functions. Both channels can operate at maximum rate in parallel.

  • Price
    		•  The PC/104p BiSerial is easily programmed to implement new functions. Many previously implemented "custom designs" are available too. Without the costs of schematic level design, layout, debugging etc. a modified BiSerial will represent a large cost savings in your budget.

  • Ease of Use
    		•  The PC/104p BiSerial is easy to use. Point and shoot - just fill the FIFO and set the start bit to get your custom protocol transmitting. Built in loop-back capabilities and engineering kits help with integration into your system. We can write a custom Windows driver for you.

  • Availability
    		•  Dynamic Engineering works to keep the PC/104p BiSerial in stock. Send in your order and in most cases have your hardware the next day. With a custom design a 1-2 week design period is usually required. We can support immediately with the -IO version then send updated PROMs later to help get your project going - right away. This design is currently in layout.

  • Size
    		•  The PC/104p BiSerial is a standard single width PC/104p card and meets the PC/104p mechanical specifications. The PC/104p BiSerial can be used in all PC/104p slots.

  • PC/104p Compatibility
    		•  The PC/104p BiSerial is PC/104p compliant per the PC/104p specification.

  • PCI Compatibility
    		•  The PC/104p BiSerial is PCI compliant. You can develop with a PCI to PC/104p adapter - PCI2PC/104p

    PC/104p-BiSerial Order Information
    1 year warranty
    Quantity discounts available
    PC/104p-BiSerial - Standard version with 16Kb FIFO per channel, standard timing
    PC/104p-BiSerial-8 - Standard version with 32Kb FIFO per channel, standard timing
    PC/104p-BiSerial-16 - Standard version with 64Kb FIFO per channel, standard timing
    PC/104p-BiSerial-32 - Standard version with 128Kb FIFO per channel, standard timing
    PC/104p-BiSerial-64 - Standard version with 256Kb FIFO per channel, standard timing
    PC/104p-BiSerial-128 - Standard version with 512Kb FIFO per channel, standard timing
    PC/104p-BiSerial-custom - custom versions with customer specified state-machines, Xilinx, and FIFOs. If your design needs less memory the internal XIlinx FIFOs can be used saving you money.
    PC/104p-BiSerial-BAE2 - RS-422 UART and Parallel port

    Engineering Kits
    Dynamic Engineering provides Engineering Kits to help our customers have a successful and quick integration. Engineering Kits will save time and money with decreased T&I. We recognize that different customers have different needs. The Engineering Kits are standardized in description to help with selection. The kits are segmented to allow for customers who only need hardware support, software support or a mixture. The Engineering Kit is highly recommended for first time buyers. The kit pricing is discounted to encourage their use.


    PC/104p-BiSerial-Eng-1 .......... Hardware Support Engineering Kit includes:
    Board level Schematics [PDF], PCI2PC104p, HDRterm50, HDRribn50

    PC/104p-BiSerial-Eng-2 .......... Hardware Support plus Driver Engineering Kit includes:
    Board level Schematics [PDF], Software[PC104p-BiSerial Driver and sample application zip file ], PCI2PC104p, HDRterm50, HDRribn50-3.

    PC/104p-BiSerial Drivers .......... Software Support Only Windows®XP and 2000 compliant drivers for the PC104p-BiSerial:


     Customer Special Versions
    You can order these too or request that we design one for you



    Related Products:
    HDRribn50 50 pin Ribbon Cable
    HDRterm50 Ribbon Cable 50 pin terminal block adapter
    PCI2PC/104p PCI to PC/104p adapter card


    You must have Adobe Acrobat 4.x to read our PDF files.
    PC104p-BiSerial-BAE2 Manual PDF


    Custom, IP, PMC, PC*MIP, PCI, VME Hardware, Software designed to your requirements



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