Embedded applications frequently require real time processing coupled with special purpose IO. With the PCIe8LXMCX2CB´s two positions a PrXMC can be matched with another XMC to make a high bandwidth processing node. The PrXMC can communicate with the host for set-up, and then use the switch to interconnect with the special purpose IO card. With a local processing node of this nature you can use many in parallel with only one computer to provide the system management. For example - 10 in an expansion chassis without overloading the buses or management system.
The CB version of PCIe8LXMCX2 has the option to connect each XMC to the standard IO, the connector bus - either, neither or both. The connector bus creates a matched length, impedance controlled, differentially routed interconnection between the two XMC positions. The bus can be used for direct connection between the cards without going through the PCIe links. High speed control, specialized communications, signal processing etc. can be faciliated by the specialized connection. Please refer to the HW manual for tables showing the connection options. Select the desired connections and submit to Dynamic Engineering. An updated machine programming file can be generated to install the desired connections to the IO and between each position. There are 64 positions for each connector. To eliminate stubs and provide the highest possible performance 4 resistors are used per IO pin. The resistors allow the Jn4/Jn6 connections to be isolated as well as the IO and CB connections. 512 possible resistors to install. Usually a subset will be installed since signals will normally be connected to Jn4 or Jn6 and not both and either IO or CB and not both.
A powerful PCIe 24 lane switch is at the center of the PCIe8LXMCX2CB design. The switch has many capabilities including operating from 1-8 lanes, operating at Gen 1 or Gen 2 or mixed IO rates, supports lane reversal and polarity inversion (in case your XMC is not quite right), Support for max payload size transfers up to 2048 bytes ea., fully compliant with the PCIe base specification 2.0. The switch has 8 PCIe lanes connected to the PCIe "gold fingers" and 8 to each of the XMC´s. The PCIe reference clock is buffered with a Gen1/Gen2 compatible clock buffer. The clock buffer is specifically designed to handle spread spectrum and rate locked clocking operation. The buffered clocks are routed to the switch and the two XMC positions. A local power supply and heavy filtering insure stable power and reliable operation for the switch. The PCIe lanes to/from the switch are routed per PCIe specifications with matched lengths and impedance control.
PCIe8LXMCX2CB (PCIexpress Bridge PMC 2 slots) adapter / carrier converter card provides the ability to install two XMC cards into a standard PCIe slot. Slots with 8 or more lanes are compatible - 8, or 16 for example. PCIe8LXMCX2CB has two XMC card positions. XMC operation with 2.5 Gbps or 5 Gbps.
PCIe8LXMCX2CB can act as a transparent switch or be programmed to allow private operations on the back side [PCIe] bus.
XMC user IO connector Pn4 or Jn6 from both positions is brought out to one of two connectors for access (DIN IDC or SCSI II). The signals corresponding to the PrXMC [position 0] standard Ethernet and Serial lines can optionally be connected to the Ethernet and Serial port connectors at the top edge of the board. The signals are isolated with resistor packs to keep the routing short. The XMC front panel connector for slot 1 is mounted though the PCIe mounting bracket.
For superior performance PCIe8LXMCX2CB has two cooling cutouts per position for increased airflow to the XMC´s. If your application requires a fan you can order
PCIe8LXMCX2CB-FAN( ) to have fans mounted to your PCIe8LXMCX2CB. FAN positions are numbered 1-4, position 1 is closest to the PCIe Bezel [left edge in the picture above.] One fan can be mounted per position. Fans can be mounted to blow onto the XMC or to pull air from the XMC (R option.)
The -12V, 5V, and 3.3V for the XMC are regulated on board. The power supply designs utilize switching regulators controlling a MOSFET to convert 12V. An LC filter ensures clean power at the XMC. The Switch uses a small amount of 3.3 and power derived from 3.3V plus 1.0V derived from +12.. The PCIe gold fingers are rated for 1.1A each, and a total of 5.5A on the +12V rail. 55W are available to the XMC´s after power conversion. Please note this is the combined power requirement across the +12, -12, +5, and 3.3V power used by the XMC´s. In most cases 55W is sufficient. PCIe8LXMCX2CB has a cable connector to allow additional 12V power to be added to the card. The two supplies are DIODE coupled. In some cases the 12V supply on the backplane will not be adequately routed by the PC causing voltage sag on the 12V. If this occurs use the cable connector to compensate.
The power supplies include the bulk capacitance to properly bypass the FET´s and post conversion voltage rails. In addition the XMC connectors are bypassed with a .1 uF capacitor at each power pin. The power supplies are checked with voltage monitor circuits. The LED´s are not illuminated unless the voltage is within the defined range. A new feature added with the current revision is the addition of two headers to allow user selection of 5V and 3.3V power on characteristics.
The user can select [with shunts] Instant On, Delayed On, and disabled. If your design does not use one of the rails you can turn it off. If your system enumerates early in the power up cycle you can select instant on. If your system can use the delayed load on the power supply to advantage select delayed.
The XMC specification calls out "VPWR " which can be either 12V or 5V. PCIe8LXMCX2CB has FET switching and a header to allow user selection of either 12V or 5V or neither voltage to be supplied to these 8 pins [per XMC]. The selection is separate per XMC position. Build options are provided to allow "pre selected" voltages on these pins without the headers. The 12V asnd 5V supplied are part of the same power budget mentioned above. It is suggested the user select the rail definition most efficient for use, alternatively based on noise, the 5V will likely be quieter since it is converted on board and isolated from the 3.3V rail.
The individual pins on the Jn4 (PN4) and Jn6 [Pn6] connectors for each slot are accessible by either a 68 pin SCSI connector or a 64 position DIN connector. The IO are routed with matched length, impedance controlled differential traces suitable for single ended and differential operation. We recommend using our SCSI cable and the
HDEterm68 breakout block with the SCSI connector. The industry standard VME IDC [DIN] connector is easy to connect to your system using
DINterm64 which is a 64 position terminal strip and the
DIN Ribbon Cable 64, a 64 position ribbon cable. The inter-connection from Jn4 and Jn6 to either the SCSI or DIN connectors are documented in the manual. Please see below.
The XMC JTAG connections for slot 0 are routed to a header. Please let us know if you want this header installed. [-JTAG]
The PCIe bus does not have a concept of global addressing. A DIPSWITCH is provided to allow the user to select the Global Address on both XMC positions individually.